Semiconductor devices typically include a drain contact, a gate, and a source contact associated with each cell of a memory array. The memory array typically including a plurality of wordlines intersected with a plurality of bitlines. In producing semiconductor devices, and more particularly FLASH memory devices, the architecture of the device should allow current to flow from the drain contact to the gate and into the source contact In making this connection, a gap is typically required in the field oxide which is utilized to isolate individual FLASH memory cells in an array of memory cells.
In past architectures, the field oxide was not made to be continuous. The field oxide stopped after a wordline in order to allow the current to pass through. However, as memory cells become progressively smaller, this method becomes progressively more difficult to perform due to a minimum field oxide size requirement to accommodate misalignment of the gate and also due to requirements of the oxide gap size in order to let the current flow through.
Another approach is to utilize a continuous field oxide, then remove a portion of the continuous field oxide to allow the current to flow through. However, other problems arise due to the additional etching step required to remove the field oxide. Since the memory array typically alternates silicon and oxide, when the oxide is etched, then the silicon is also typically exposed to the etch. Although the etching material typically has a high selectivity, i.e., the oxide is etched much faster than the silicon, some of the silicon will still be etched away. When the silicon is damaged, reliability problems can be created for the FLASH memory device.
One solution is presented in U.S. Pat. No. 5,470,773 issued Nov. 28, 1995, to Liu et al. In the Liu patent, a method is described in which oxide spacers on the side wall of the gate is utilized to reduce the area of damage to the silicon. Although the Liu method works well for many applications, as the memory cells become smaller, the space between the gates become narrower. Consequently, it becomes more difficult to place spacers next to the gate.
An additional parameter to be met is that the spacer width typically needs to be a certain width as determined by transistor performance for n-channel, p-channel and electronic sensitive device (ESD) transistors used in the peripheral circuit. To meet this parameter, oxide spacer deposition can be performed in multiple stages. For instance, a first spacer oxide may be deposited at half the required spacer width. Then, the first spacer is etched in the core area only and a second spacer oxide may be deposited. Thereafter, both spacer oxides are etched together in the periphery circuit, but only the second spacer oxide will be etched in core area.
Although this method appears to work well for some cells, such as source spacing in cells wider than 0.4 microns, the second oxide spacer layer may, however, be pinched between gates for source spacing in cells smaller than 0.4 microns. Another problem associated with this method is caused by the first layer of oxide spacer on the peripheral circuit not being etched and protected by a photoresist, while the first layer of oxide spacer on the core area of the memory are being etched. Consequently, when the second layer of oxide spacer is etched, the peripheral circuit will have double the thickness of oxide spacer than the core area of the memory. When the first half of the oxide spacer in the periphery area are etched away, the etch for the remaining half of the oxide spacer in the periphery area now begins to etch the silicon in the core area, since the core area only has half the thickness of the oxide spacer in the peripheral area. Consequently, the damaged silicon creeps closer to the edge of the gate.
Accordingly, what is needed is a semiconductor device and a method for providing such a semiconductor device which causes a gap in the field oxide to allow the current to flow through, while minimizing the damage caused to the silicon by the field oxide etching process. The present invention addresses such a need.